1. Field of the Invention
The present invention relates to a test mode circuit incorporated into a semiconductor memory device such as synchronous dynamic random access memory (SDRAM) device.
2. Description of the Related Art
In a test mode circuit incorporated into a SDRAM device, a latch circuit latches a test enable signal and address signals, and a decoder circuit decodes the address signals latched in the latch circuit in response to the test enable signal latched in the latch circuit to generate one of test mode signals. Also, a power on reset signal generating circuit is provided. A gate circuit controlled by the power on reset signal generating circuit is connected between the latch circuit and the decoder circuit. Therefore, when the power on reset signal is generated from the power on reset signal generating circuit, the gate circuit stops the transfer of the test enable signal and the address signals from the latch circuit to the decoder circuit, thus resetting the test mode signals. This will be explained later in detail.
In the above-described prior art test mode circuit, whether or not the power on reset signal is generated depends on the rising waveform of the power supply voltage. Therefore, even if the power is turned ON, the power on reset signal generating circuit does not surely generate a power-on-reset signal. As a result, even after the power is turned ON, the device may enter a normal operation mode without resetting the test mode signals. In this case, the normal operation mode becomes erroneous. In addition, since it is impossible for the user to reset the test modes from the exterior of the device, the device can never enter a normal operation mode.
It is an object of the present invention to provide a test mode circuit capable of surely resetting test mode signals.
According to the present invention, in a test mode circuit, a latch circuit latches a test enable signal and address signals, and a decoder circuit decodes the address signals latched in the latch circuit in response to the test enable signal latched in the latch circuit to generate one of the test mode signals. A data mask terminal is connected to an input circuit for inputting a signal at the data mask terminal and generating a mask signal. A gate circuit is connected to the latch circuit or the decoder circuit and the input circuit. The gate circuit passes the test enable signal and the address signals or the test mode signals when the mask signal is inactive, and masks the same signals when the mask signal is active.